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www.irf.com ? 2008 international rectifier august 8, 2011 irs2113mpbf high- and low-side driver features ? floating channel designed for bootstrap operation ? fully operational to +600 v ? tolerant to negative transient voltage C dv/dt immune ? gate drive supply range from 10 v to 20 v ? undervoltage lockout for both channels ? 3.3 v input logic compatible ? separate logic supply range from 3.3 v to 20 v ? logic and power ground 5 v offset ? cmos schmitttriggered inputs with pulldown ? cycle by cycle edgetriggered shutdown logic ? matched propagation delay for both channels ? output in phase with inputs ? leadfree, rohs compliant description the irs2113mpbf is a high voltage, high speed power mosfet and igbt drivers with independent high and low side referenced output channels. proprietary hv ic and latch immune cmos technologies enable ruggedized monolithic construction. the logic input is compatible with standard cmos or lsttl output, down to 3.3 v logic. the output drivers feature a h igh pulse current buffer stage designed for minimum dri ver crossconduction. propagation delays are matched to simplify use in high frequency applications. the fl oating channel can be used to drive an nchannel power mosfet or igbt in the high side configuration which operates up to 600 v. product summary topology 2 channels v offset 600 v max v out 10 v C 20 v i o+ & i o (typical) 2.5 a / 2.5 a t on & t off (typical) 130 ns & 120 ns delay matching 20 ns max package option mlpq4x416lead (without 2 leads) typical connection diagram (refer to leads assignment for correct pin configur ations) this diagram shows electrical connections o nly. please refer to our application notes and design ti ps for proper circuit board layout.
irs2113mpbf www.irf.com ? 2008 international rectifier 2 qualification information ? industrial ?? (per jedec jesd 47) qualification level comments: this ic has passed jedecs industrial qualification. irs consumer qualification level i s granted by extension of the higher industrial level . moisture sensitivity level mlpq4x4 14l msl2 ??? (per ipc/jedec jstd 020) machine model class a (+/200v) (per jedec standard jesd22a115) human body model class 1b (+/1000v) (per eia/jedec standard eia/jesd22a114) esd charged device model class iii (+/1000v) (per jedec standard jesd22c101) ic latch-up test class ii, level a (per jesd78a) rohs compliant yes ? qualification standards can be found at internation al rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sales represen tative for further information. ??? higher msl ratings may be available for the specifi c package types listed here. please contact your international rectifier sales representative f or further information.
irs2113mpbf www.irf.com ? 2008 international rectifier 3 recommended operating conditions the input/output logic timing diagram is shown in f igure 1. for proper operation the device should be used within the recommended conditions. the v s and v ss offset rating are tested with all supplies biased at 15 v differential. ? logic operational for v s of 4 v to +500 v. logic state held for v s of 4 v to C v bs. (please refer to the design tip dt97 3 for more de tails). ?? when v dd < 5 v, the minimum v ss offset is limited to Cv dd . absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounte d and still air conditions. symbol definition min. max. units v b highside floating supply voltage 0.3 625 v s highside floating supply offset voltage v b 20 v b + 0.3 v ho highside floating output voltage v s 0.3 v b + 0.3 v cc lowside fixed supply voltage 0.3 25 v lo lowside output voltage 0.3 v cc + 0.3 v dd logic supply voltage 0.3 v ss + 20 ( ? ) v ss logic supply offset voltage v cc 20 v cc + 0.3 v in logic input voltage (hin, lin & sd) v ss 0.3 v dd + 0.3 v dv s /dt allowable offset supply voltage transient (fig. 2) 50 v/ns p d package power dissipation @ ta 25c 2.08 w rth ja thermal resistance, junction to ambient 36 c/w t j junction temperature 150 t s storage temperature 55 150 t l lead temperature (soldering, 10 seconds) 300 c ? all supplies are fully tested at 25 v, and an inter nal 20 v clamp exists for each supply. symbol definition min. max. units v b highside floating supply absolute voltage v s +10 v s +20 v s highside floating supply offset voltage ? 600 v ho highside floating output voltage v s v b v cc lowside fixed supply voltage 10 20 v lo lowside output voltage 0 v cc v dd logic supply voltage v ss + 3 v ss + 20 v ss logic ground offset voltage 5 ( ?? ) 5 v in logic input voltage (hin, lin & sd) v ss v dd v t a ambient temperature 40 125 c
irs2113mpbf www.irf.com ? 2008 international rectifier 4 static electrical characteristics v bias (v cc , v bs, v dd ) = 15 v, t a = 25c and v ss = com unless otherwise specified. the v il, v th and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin and sd. the v o, and i o parameters are referenced to com and are applicabl e to the respective output leads: ho or lo. dynamic electrical characteristics v bias (v cc , v bs, v dd ) = 15 v, c l = 1000 pf, t a = 25c and v ss = com unless otherwise specified. the dynamic electrical characteristics are measured usi ng the test circuit shown in fig. 3. symbol definition min typ max units test conditions v ih logic 1 input voltage 9.5 v il logic 0 input voltage 6.0 v oh high level output voltage, v bias v o 1.4 i o = 0 a v ol low level output voltage, v o 0.15 v i o = 20 ma i lk offset supply leakage current 50 v b = v s = 600 v i qbs quiescent v bs supply current 125 230 i qcc quiescent v cc supply current 180 340 i qdd quiescent v dd supply current 15 30 v in = 0 v or v dd i in+ logic 1 input bias current 20 40 v in = v dd i in logic 0 input bias current 5.0 a v in = 0 v v bsuv+ v bs supply undervoltage positive going threshold 7.5 8. 6 9.7 v bsuv v bs supply undervoltage negative going threshold 7.0 8. 2 9.4 v ccuv+ v cc supply undervoltage positive going threshold 7.4 8. 5 9.6 v ccuv v cc supply undervoltage negative going threshold 7.0 8. 2 9.4 v i o+ output high short circuit pulsed current 2.0 2.5 v o = 0 v, v in = v dd pw 10 us i o output low short circuit pulsed current 2.0 2.5 a v o = 15 v, v in = 0 v pw 10 us symbol definition min typ max units test conditions t on turnon propagation delay 130 200 v s = 0 v t off turnoff propagation delay 120 190 t sd shutdown propagation delay 130 160 v s = 600 v t r turnon rise time 25 35 t f turnoff fall time 17 25 mt delay matching, hs & ls turn on/off 20 ns
irs2113mpbf www.irf.com ? 2008 international rectifier 5 functional block diagram
irs2113mpbf www.irf.com ? 2008 international rectifier 6 input/output pin equivalent circuit diagrams
irs2113mpbf www.irf.com ? 2008 international rectifier 7 lead definitions pin symbol description 1 v dd logic supply 2 hin logic input for highside gate driver output (h o), in phase 3 sd logic input for shutdown 4 lin logic input for lowside gate driver output (lo ), in phase 5 v ss logic ground 6 lo lowside gate drive output 7 com lowside return 8 nc no connection 9 v cc lowside supply 10 nc no connection (pin removed) 11 nc no connection 12 v s highside floating supply return 13 v b highside floating supply 14 ho highside gate drive output 15 nc no connection (pin removed) 16 nc no connection lead assignments irs2113mpbf 16lmlpq 4x4 with 2 leads removed = removed lead 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vdd hin sd lin vs vcc nc irs2113mpbf nc
irs2113mpbf www.irf.com ? 2008 international rectifier 8 application information and additional details 1 2 3 45 6 7 9 12 13 14 10 f 0.1 f v cc = 15 v 0.1 f ho 10 f 10 f v b v s ( o v to 600v ) 15 v lo c l c l hin sd lin figure 2 : floatin g supply voltage transient test circuit figure 3: switching time test circuit figure 1: input/output timing diagram
irs2113mpbf www.irf.com ? 2008 international rectifier 9 figure 4: switching time waveform definitions figure 6 : delay matching waveform definitions figure 5: shutdown waveform definitions
irs2113mpbf www.irf.com ? 2008 international rectifier 10 parameter temperature trends
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irs2113mpbf www.irf.com ? 2008 international rectifier 19 package details: mlpq 4x4 -16l
irs2113mpbf www.irf.com ? 2008 international rectifier 20 tape and reel details: mlpq 4x4
irs2113mpbf www.irf.com ? 2008 international rectifier 21 part marking information: ordering information standard pack base part number package type form quantity complete part number tube/bulk 92 irs2113mpbf irs2113 mlpq 4x416l tape and reel 3,000 IRS2113MTRPBF the information provided in this document is believ ed to be accurate and reliable. however, internatio nal rectifier assumes no responsibility for the consequences of the use of t his information. international rectifier assumes n o responsibility for any infringement of patents or of other rights of third parties which may result from the use of this info rmation. no license is granted by implication or otherwise under any patent or pat ent rights of international rectifier. the specifi cations mentioned in this document are subject to change without notice. thi s document supersedes and replaces all information previously supplied. for technical support, please contact irs technica l assistance center http://www.irf.com/technicalinfo/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 2527105
irs2113mpbf www.irf.com ? 2008 international rectifier 22 revision history date comment 09/24/09 initial conversion from so package style d ata sheet 03/24/2010 included qual info page 08/08/2011 update the package details

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